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Asynchronous Logic Ring Oscillator

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  • Circuit research/design in drapht.
Phase switch layout rail-mounted sockets 1059x742.png

April 11, 2013 (MDT)

  • A ring amp made with three flip-flop latches shown in Fig. 1 oscillates with a period of 0.00000008 sec., or 1 x 10-8 cycle period.
  • The frequency of this period is 12,500,000 Hz, or 1.25 x 107 Hz.
  • The TTL device was a 74HC00 Quad NAND gate plastic 14-pin DIP packages on a breadboard layout.

June 2013

  • Ten days with Captain Caveman[1] revealed a complete story, sketchy in scope, but sufficient in technical details to warrant a scientific investigation into the claims of an apparently crazy individual [2]. Ten days with family yielded about a dozen recorded sessions of technical and theoretic details toward fulfillment of a scientific urgency.

  1. Ten days of disclosure briefings were hosted by the Capt.'s sister.
  2. The family noticed a big change in David when he began experimenting with a device akin to the purpose of the device of Fig. 1.

July 12, 2013

Fig. 2. Nine Villarceaux circles arranged as a torus of orthogonal dynamics to a momenta pair whose ratio is the golden ratio (almost).
  • Time since a visit with the Capt. has been a chaotic melding of concepts that I need to own in a personal sense. Owning knowledge is to test knowledge in practice as regularly dependable. Owned knowledge becomes a personal truth.
  • About yesterday I realized the obvious —my interest basins have each been snap-fitting into this project with epiphany-class gee wiz excitement. I've seen digital circuitry having a large role in designs to be reckoned, but the concept just arrived that puts the first version exactly as an ascynchronous logic ring oscillator, with data collection occurring at the same logic layer (no translation or sensor hardware needed). This is afforded by using a TTL-level high-speed driver chip (8-pin DIP) with a 15 nanosecond rise-time designed for charging power MOSFET gates.
  • The first version has emerged as an Asynchronous Logic Ring Oscillator. This oscillator will be able to populate a data storage memory directly from the asynchronous timing of the pulse-edges of the logic oscillator. This will create a data set for analysis after the fact.
  • As the approach for data analysis is the creation of a data-log of the timing profile of the asynchronous jitter in the ring oscillator stages. Each stage is a common flip-flop of NAND gates (74HC00N, a high-speed CMOS work-alike to the original TTL quad NAND gate logic chip (7400 by TI, originally). This design will focus upon maximizing the frequency of a quartz oscillator as a time-base, and recording the quartz-time from a binary-counter-buss each time a flip-flop changes state within the ring of three flip-flop stages. The data size will then be limited to the amount of memory available as data storage (flip-time log), and a function of the frequency of ring oscillator flip events.
  • Early thoughts on the the frequency of the clock needed for a precision timing of the jitter in a noisy three-phase oscillation:
  1. Ten-parts resolution of the phase-jitter of the Asynchronous Logic Ring Oscillator seems a practical goal for the first design. Versions will evolve as data trends indicate.
  2. Ten-parts resolution of a 360 degrees / 3 phases = 12 degrees per phase resolution on edge jitter travel within the rotary phase space.
  3. Ten-part resolution of a wavelength requires a frequency ten time higher than the base wavelength of the 3-phase frequency established by the pulse-chase within the logic-ring.
  • For an application as a chaotic ring oscillator finding a basin attractor within EM dynamics approaching Znidarsic's velocity (invoking a nucleosonic coupling) on a coherent topology. The Z-velocity = 1.094 'meter-seconds' X 106 meter-seconds.
  • Various topologies as velocity-domains on the torus-form of the Villarceaux circle resonator design:
  1. The inner circumference of the torus hole.
  2. The outer circumference of the torus on the torus plane.
  3. The circumference of the Villarceaux circle driver coil (a slanted cross-section of the torus form).
  • The worst-case, or highest frequency needed to achieve the Z-velocity, setting the target frequency range of the quartz time-base to obtain the resolution needed, would be the smaller of the candidate resonant topologies listed above.
  • The small torus hole in the Villarceaux circle design fabricated (See Fig. 2) has a hole radius (R-r) of 0.38", and a hole circumference of about 2 × π × 0.38" = 2.40" (measured from the hollow conductor centers).
  • The frequency needed to achieve the lineal motion of the Z-velocity by the resonant phase geometry is then:
1.094×106meter-seconds ÷ (2.40" ÷ 25.4 inch/meter) = 16.4 megaHertz
  • This anticipated highest frequency of 3-phase-rotation around the torus-hole, in step-phase progression of nine rings, would be a frequency three times higher, 3 × 16.4 megaHertz = 49.2 megaHertz base frequency of the 3-phase rotary progression.

  • The worst-case frequency of operation for TTL logic circuits used in the flip-flop ring would be above the 12.5 megaHertz capability of a 3-stage NAND-gate ring oscillator tested on a breadboard. A nine-stage oscillator would be three times worse, only able to obtain 4 megaHertz based on test results with the 3-stage ring.